The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices necessitate design features of 0.18 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.18 microns and under challenges the limitations of conventional semiconductor manufacturing techniques.
As design features shrink to less than about 0.18 microns, it is necessary to significantly reduce the depth of the source and drain regions below the surface of the semiconductor substrate, particularly the lightly doped source/drain (LDD) regions, i.e., the junction depth (X.sub.J). For example, in forming a polycrystalline silicon gate having a width of about 0.18 microns and under, the junction depth (X.sub.J) should not exceed about 700 .ANG. for reducing short channel effects associated with small gate length MOSFETs. However, the formation of a shallow X.sub.J less than about 700 .ANG. exhibiting low-sheet resistance employing conventional semiconductor manufacturing methodology is problematic.
Conventional methodology comprises implanting boron (B) or boron difluoride (BF.sub.2) into regions of a crystalline silicon semiconductor substrate and activation annealing to form P-type source/drain regions. B ions are implanted at an energy selected to determine the eventual X.sub.J, and at a dosage selected to control the desired concentration. As B is an extremely light element, it must be implanted at a very low energy in order to achieve a shallow X.sub.J. Accordingly, B is typically implanted at an energy of about 5 KeV.
It has been found, however, that B and BF.sub.2 exhibit considerable channeling even during relatively low energy ion implantation. In addition, upon subsequent activation annealing, B and BF.sub.2 diffusion through crystalline silicon proceed apace, such that the junction depth of B exceeds the target X.sub.J of no greater than about 700 .ANG.. The problem of undefined X.sub.J is believed to stem from various factors, including channeling and diffusion. For example, B implantation is believed to damage the monocrystalline silicon substrate generating interstitial silicon (Si) atoms, i.e., Si atoms that are displaced from the monocrystalline lattice to occupy spaces between Si atoms in the monocrystalline lattice. During the high temperature activation anneal, B diffuses into the monocrystalline Si layer by attaching to the generated interstitial Si atoms, causing an extremely rapid diffusion of B into the monocrystalline Si layer. Such a rapid B diffusion causes the dopant profile and, hence, X.sub.J, to extend below the targeted maximum of 700 .ANG., i.e., to a X.sub.J of about 2000 .ANG. or deeper, notwithstanding the low initial implantation energy of about 5 KeV.
A previous approach to the undefined X.sub.J problem is disclosed in copending application Ser. No. 08/726,113 and comprises initially forming a surface amorphous region in the monocrystalline Si substrate. The surface amorphous region is formed by ion implanting appropriate neutral impurities, such as germanium (Ge) or Si. B is then ion implanted into the essentially amorphous Si region which does not contain any appreciable amount of interstitial Si atoms to which B would otherwise attach. Accordingly, upon subsequent activation annealing, rapid diffusion of B by transient enhanced diffusion is not significant due to the substantial lack of interstitial Si atoms. Therefore, the X.sub.J can be controlled by appropriate selection of the implantation energy. During activation annealing, the amorphous region is crystallized by solid phase epitaxy.
It was found, however, that end-of-range damage, e.g., defects comprising dislocations and stacking faults, occurs upon crystallization of the surface amorphous region during activation annealing. Such end-of-range defects are present in a subsequently formed depletion layer resulting in leakage. In copending application Ser. No. 08/992,629 a method is disclosed wherein a sub-surface, non-amorphous region is formed before activation annealing to substantially eliminate end-of-range defects generated upon crystallization of a shallow amorphous region containing the lightly doped implants.
Continued miniaturization below 0.18 microns necessitates reliable formation of ultra shallow but low-resistant junctions to achieve low off-state leakage by suppressing the short channel effects and a high drive current. Accordingly, there exists a need for semiconductor methodology enabling the formation of low resistance, shallow LDD junctions with reduced channeling and reduced transient enhanced diffusion. There exists a particular need for semiconductor technology enabling the formation of low resistance, ultra shallow LDD junctions having an acceptable leakage current and substantially reducing or eliminating transient enhanced diffusion linked to the generation of an interstitial-rich region attendant upon LDD implantation.